View 82547GI_2788241.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

82562ez(ex)/82547GI(ei) dual footprint design guide networking silicon 317520-002 revision 2.2
ii information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the product(s) described in this document may contain design defects or errors known as errata which may cause the product to d eviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature, may be obtain ed from: intel corporation p.o. box 5937 denver, co 80217-9808 or call in north america 1-800-548-4725, europe 44-0-1793-431-155, france 44-0-1793-421-777, germany 44-0-1793-421-333, other c ountries 708- 296-9333. intel? is a trademark or registered trademark of intel corporation or its subsidiaries in the united states and other countries . copyright ? intel corporation, 2008 *third-party brands and names are the property of their respective owners.
iii 82562ez(ex)/82547GI(ei) dual footprint revision history revision revision date description 0.25 jul 2002 initial publication of preliminary design guide information. 0.75 sep 2002 published revised design guide information: added information on eeprom settings added design checklist revised reference design schematic revised ball number to signal mapping table to conform to changes in 82547ei datasheet rev 0.75 1.0 oct 2002 published revised design guide information: added layout checklist updated lan disable circuit removed eeprom information due to publication of separate guides 1.5 sep 2003 published revised design guide information: added 82547GI coverage removed confidential status updated schematics, removed redundant caps revised lan disable circuit 1.6 nov 2004 added crystal start-up information. information includes: new crystal parameters crystal selection guidelines crystal validation methods crystal testing methods changed signal name fl_so to the correct signal name flsh_so. added 82562ex applicability. added new values for tx and rx terminations (next to lan silicon). new values are now 110 ? for both tx and rx terminations. added new starting values for rbias100 and rbias10. new starting values are now 649 ? for rbias100 and 619 ? for rbias10. updated reference schematics to reflect new tx and rx termination values, new lan disable circuit, and rbias100/rbias10 values. removed excess capacitors and changed pins f12 and h12 to no connects. added a 1k ? resistor to pin a13 output. 1.7 jan 2005 changed text in the catalyst eeprom revision h table note from ?revision h or higher not supported? to ?revisi on h is not supported?. removed the design and layout check lists. these checklists are now separate microsoft* excel spreadsheets. 1.8 jan 2005 updated reference schematics to refl ect current differential pair termination resistor values for the 82547GI/ei. updated section 4.2.1 ?termination resistors for designs based on 82562ez/ ex plc device? to reflect current resistor and rbias values. updated section 4.3.1 ?termination resistors for designs based on 8257gi(ei) gigabit ethernet controller? to reflect current resistor values. 1.9 june 2006 updated reference schematics for signals ee_mode and jtag_trst# (changed resistor values from 1 k ? to 100 ? ). 2.0 feb 2007 updated sections 3.1.3, 3.1.1.8, and table 5 in section 3.1.1 (changed max esr rate from 20 ? to 10 ? for the 82547GI/ei). 2.1 june 2007 updated reference schematics: sheets 4 and 6. 2.2 jan 2008 added table 6; approved crystals for the 82547GI(ei).
iv 82562ez(ex)/82547GI(ei) dual footprint note: this page is intentionally left blank.
v 82562ez(ex)/82547GI(ei) dual footprint design guide contents 1.0 introduction................................................................................................................ ......... 1 1.1 scope....................................................................................................................... ..................... 1 1.2 reference documents ......................................................................................................... ......... 2 1.3 product codes ............................................................................................................... ............... 2 2.0 system data port interfaces .............................................................................................. 3 2.1 lci connection to 82562ez(ex) platform lan connect device ................................................. 3 2.2 csa port connection to 82547GI(ei) gigabit ethernet controller ............................................... 4 2.2.1 generation/distribution of reference voltages ............................................................... 4 2.2.2 csa port resistive compensation .................................................................................. 5 3.0 ethernet component design guidelines ............................................................................ 7 3.1 general design considerations for ethernet controllers.............................................................. 7 3.1.1 crystal selection parameters .......................................................................................... 7 3.1.2 reference crystal ......................................................................................................... .10 3.1.3 reference crystal selection ..........................................................................................11 3.1.4 circuit board ............................................................................................................. .....11 3.1.5 temperature changes...................................................................................................11 3.1.6 integrated magnetics module ........................................................................................12 3.2 designing with the 82562ez(ex) platform lan connect device...............................................12 3.2.1 82562ez/ex plc device lan disable guidelines .......................................................12 3.2.2 serial eeprom for 82562ez(ex) implementations......................................................13 3.2.3 magnetics modules for 82562ez(ex) plc device........................................................14 3.2.4 power supplies for 82562ez(ex) plc implementations ..............................................14 3.2.5 82562ez(ex) device test capability ............................................................................14 3.3 designing with the 82547GI(ei) gigabit ethernet controller ......................................................14 3.3.1 82547GI(ei) ethernet controller lan disable guidelines .............................................14 3.3.2 serial eeprom for 82547GI(ei) controller implementations .......................................15 3.3.3 eeprom map information ............................................................................................17 3.3.4 magnetics modules for 82547GI(ei) controller applications .........................................17 3.3.5 power supplies for the 82547GI(ei) device ..................................................................17 3.3.6 82547GI(ei) controller power supply filtering..............................................................18 3.3.7 82547GI(ei) controller power management and wake up...........................................18 3.3.8 82547GI(ei) device test capability ..............................................................................19 4.0 ethernet component layout guidelines ..........................................................................21 4.1 general layout considerations for ethernet controllers ............................................................21 4.1.1 guidelines for component placement ...........................................................................21 4.1.2 crystals.................................................................................................................. ........22 4.1.3 board stack up recommendations...............................................................................22 4.1.4 differential pair trace routing.......................................................................................23 4.1.5 signal trace geometry..................................................................................................24 4.1.6 trace length and symmetry .........................................................................................24 4.1.7 impedance discontinuities.............................................................................................25 4.1.8 reducing circuit inductance..........................................................................................25 4.1.9 signal isolation .......................................................................................................... ....25 4.1.10 power and ground planes.............................................................................................25
vi 82562ez(ex)/82547GI(ei) dual footprint design guide 4.1.11 traces for decoupling capacitors ................................................................................. 26 4.1.12 ground planes under the magnetics module................................................................ 26 4.1.13 special considerations for non-integrated magnetics modules and rj-45 connectors................................................................... 28 4.2 layout for the 82562ez(ex) platform lan connect device ...................................................... 29 4.2.1 termination resistors for designs based on 82562ez(ex) plc device...................... 29 4.2.2 light emitting diodes for designs based on 82562ez(ex) plc device....................... 29 4.3 layout for the 82547GI(ei) gigabit ethernet controller ............................................................. 30 4.3.1 termination resistors for designs based on 82547GI(ei) gigabit ethernet controller 30 4.3.2 light emitting diodes for designs based on 82547GI(ei) controller ............................ 30 4.4 physical layer conformance testing ......................................................................................... 3 0 4.5 troubleshooting common physical layout issues..................................................................... 31 5.0 design and layout checklists.......................................................................................... 33 6.0 ball number to signal mapping with population options................................................. 35 7.0 dual footprint reference schematic ............................................................................... 43 a measuring lan reference frequency using a frequency counter................................ 51 b gigconf.exe register settings for 82547GI(ei) devices ................................................. 57 figures 1 ich5 platform lan connect sections .......................................................................................... 3 2 csa port locally generated reference divider circuits.............................................................. 4 3 csa port ci_rcomp circuits .................................................................................................... .. 5 4 crystal circuit ............................................................................................................... ................ 9 5 lan disable circuitry ......................................................................................................... ........ 13 6 82547GI(ei) lan disable circuitry ............................................................................................. 15 5 general placement distances ................................................................................................... .22 6 trace routing ................................................................................................................. ............ 23 7 ground plane separation ....................................................................................................... .... 26 8 ideal ground split implementation ............................................................................................. 27 9 termination plane example for 82562ez(ex) plc device and discrete magnetics ................. 28 10 82562ez(ex) plc device differential signal termination......................................................... 29 11 indirect probing setup ....................................................................................................... ......... 52 12 direct probing method ........................................................................................................ ........ 55
vii 82562ez(ex)/82547GI(ei) dual footprint design guide tables 1 lan component connections/features ....................................................................................... 1 2 product ordering codes ........................................................................................................ ....... 2 3 csa port reference circuit specifications................................................................................... 4 4 csa port ci_rcomp resistor values......................................................................................... 5 5 crystal parameters ............................................................................................................ ........... 7 6 82547GI(ei) recommended crystals...........................................................................................8 7 82562ez(ex) memory layout (128 byte eeprom) ..................................................................13 8 82562ez(ex) memory layout (512 byte eeprom) ..................................................................14 9 82562ez(ex) recommended magnetics modules.....................................................................14 10 microwire 64 x 16 serial eeproms ...........................................................................................16 11 spi serial eeproms for 82547GI(ei) controller .......................................................................16 12 82547GI(ei) eeprom memory layout......................................................................................17 13 82547GI(ei) recommended magnetics modules.......................................................................17 14 ball number to signal mapping ................................................................................................ ..35
viii 82562ez(ex)/82547GI(ei) dual footprint design guide note: this page intentionally left blank.
82562ez(ex)/82547GI(ei) dual footprint design guide 1 1.0 introduction intel currently supports several footprint compatible ethernet options depending upon the target application. the term ?footprint compatible? means that the silicon devices are all manufactured in a 15 mm x 15 mm, 196-ball grid array package with the same ball pattern. many of the critical signal pin locations are identi cal, allowing designers to create a single lan on motherboard (lom) design that accommodates all devices. this is a flexible, cost-effective, multipurpose design technique that allowing maximized value while matching performance needs. note: since some of the signal pins have different us ages, the term ?pin-compa tible? is not applicable. available lan components with the same footprint include the 82547GI(ei) gigabit ethernet controller and the 82562ez(ex) platform lan connect components. the lan component used on a specific platform depends on the end user?s need for connection speed and manageability. as the requirements change, footprint compatibility makes it possible to re-focus the platform without the need to redesign a new a motherboard. 1.1 scope this application note contains ethernet design gu idelines applicable to lom designs based on the intel ? 865 chipset and intel ? 875 chipset. the document identifies similarities and differences between the 82562ez(ex) platform lan connect device and the 82547GI(ei) gigabit ethernet controller. section 2 describes the port interfaces specific to each device. section 3 explains what you need to know to hook up an ethernet device to the system. section 4 describes board layout techniques applicable to these devices. section 5 provides a reference to the design and layout checklists. table 1. lan component connections/features lan component interface connection features intel ? 82547GI(ei) csa gigabit ethernet (1000base-t) with alert standard format (asf) alerting gigabit ethernet, asf 2.0 alerting intel ? 82562ex (196 bga) lci 10/100 ethernet with asf alerting ethernet 10/100 connection, asf 1.0 alerting intel ? 82562ez (196 bga) lci basic 10/100 ethernet ethernet 10/100 connection
82562ez(ex)/82547GI(ei) dual footprint design guide 2 section 6 compares pin names and numbers between the two components. section 7 concludes with a reference design schematic of the full dual footprint configuration. note: it is assumed that the reader is acquainted with high-speed design and board layout techniques. additional documents may be referred to for further information. 1.2 reference documents 82547GI(ei) gigabit ethernet controller datasheet. intel corporation. 82562ez 10/100 mbps platform lan connect (plc) networking silicon datasheet. intel corporation. 82562et/em platform lan connect printed circuit board design guide. intel corporation. 82547GI(ei)/82541(pi/gi/ei)/82541er eeprom map and programming information. intel corporation. ich2 integrated lan controller function disable and power control. intel corporation. pci bus power management interface specificatio n, rev. 1.1, pci special interest group. ieee standard 802.3, 2000 edition. incorporates various ieee standards previously published separately. i/o control hub 2, 3, and 4 eeprom map and programming information. intel corporation. i/o control hub 5, 6, and 7 eeprom map and programming information. intel corporation. programming information can be obtained through your local intel representative. 1.3 product codes table 2 lists the product ordering codes for the 82562ez(ex)and 82547GI(ei). table 2. product ordering codes device product code product code (lead free) 82562ez gd82562ez lu82562ez 82562ex gd82562ex lu82562ex 82547GI gd82547GI lu82547GI 82547ei gd82547ei lu82547ei
82562ez(ex)/82547GI(ei) dual footprint design guide 3 2.0 system data port interfaces the 82562ez(ex) platform lan connect device and the 82547GI(ei) gigabit ethernet controller employ different system interfaces, as illustrated in figure 1 . figure 1. ich5 platform lan connect sections 2.1 lci connection to 82562ez(ex) platform lan connect device the 82562ez(ex) platform lan connect device uses the lan connect interface (lci) to connect to the i/o control hub 5 (ich5). lci is a point-to-point interface optimized to support one device. line termination mechanisms are not specified fo r the lci. slew rate controlled output buffers achieve acceptable signal integrity by controlling signal reflection, undershoot and ringing. for details about how to connect the lci in terface between the 82562ez(ex) platform lan connect device and ich5, please refer to the 825 62et/em platform lan connect printed circuit board (pcb) design guide, the intel ? 865 chipset design guide, or the intel ? 875 chipset design guide. gmch magnetics module connector intel ? 82562ez(ex) intel? ich5 lci intel ? 82547GI(ei) csa
82562ez(ex)/82547GI(ei) dual footprint design guide 4 2.2 csa port connection to 82547GI(ei) gigabit ethernet controller the 82547GI(ei) gigabit ethernet controller us es the communications streaming architecture (csa) port to connect to the memory control hub (mch). csa is a point-to-point interface supporting one device. csa has a theoretical bandwidth of 266 mb/s, sufficient to support gigabit ethernet speeds. the connection to the mch places the ethernet cont roller close to system memory for minimum latency. the csa interface uses igtl buffers to achieve very high data speeds while controlling transmission line characteristics. for details on connecting the csa interface between the 82547GI(ei) gigabit ethernet controller and the mch, please refer to the intel ? 865 chipset design guide, or the intel ? 875 chipset design guide. 2.2.1 generation/distribution of reference voltages the 11-bit csa port on the 82547GI(ei) controller has a dedicated ci_vref pin to sample the reference voltage. the nominal csa port reference voltage is 0.35 v 3%. in addition to the reference voltage, a reference swing voltage, ci_swing must be supplied to control buffer voltage swing characteristics. the nominal csa port reference voltage swing must be 0.8 v 3%. figure 2. csa port locally generated reference divider circuits table 3. csa port reference circuit specifications reference voltage specification (v) reference swing voltage specification (v) 1.2 v voltage divider circuit recommended resistor values ( ? ) 0.350 3% 0.8 3% r1 = 523 1% r2 = 665 1% r3 = 604 1% intel? 82547GI(ei) 0.35 v 0.8 v ci_swing ci_vref r1 r2 r3 c2 c1 c1 c2 1.2v
82562ez(ex)/82547GI(ei) dual footprint design guide 5 the values of r1, r2 and r3 must be rated at 1% tolerance. the selected resistor values must also ensure that the reference voltage and reference swing voltage tolerance are maintained over the input leakage specification. a 0.1 f capacitor (c1 in figure 2 ) should be placed within 0.5 inches to each resistor divider, and a 0.01 f bypass capacitor (c2 in figure 2 ) should be placed within 0.25 inches of reference voltage pins. if the length of the trace from the voltage divider to the pin is greater than 1 inch, place more than one 0.01 f capacitor near the reference voltage pin. the trace length from the voltage divider circuit to the ci_ref pins must be no longer than 3.5 inches. both the voltage reference and voltage swing reference signals should be routed at least 10mils wide and spaced at least 20 mils from all other signals. 2.2.2 csa port resistive compensation the csa port uses a resistive compensation si gnal (ci_rcomp) to compensate buffer characteristics for temperature, voltage, and process. figure 3. csa port ci_rcomp circuits table 4. csa port ci_rcomp resistor values component trace impedance rcomp resistor value rcomp resistor tied to intel ? 82547GI(ei) 60 ? 15% r1 = 30.1 ? 1% vcc1.2 r1 1.2v intel? 82547GI(ei) ci_rcomp
82562ez(ex)/82547GI(ei) dual footprint design guide 6 note: this page intentionally left blank.
82562ez(ex)/82547GI(ei) dual footprint design guide 7 3.0 ethernet component design guidelines these sections provide recommendations for selecting components and connecting special pins. the main design elements are the 82562ez( ex) platform lan connect device or the 82547GI(ei) gigabit ethernet controller, an integrated magnetics module with rj-45 connector, and a crystal clock source. 3.1 general design considerations for ethernet controllers these recommendations apply to all designs, 10/100 or 10/100/1000 mb/s. follow good engineering practices with respect to unused inputs by terminating them with pull-up or pull-down resistors, unless the data sheet, design guide or reference schematic indicates otherwise. do not attach pull-up or pull-down resistors to any balls identified as no connect. these devices may have special test mode s that could be entered inadvertently. 3.1.1 crystal selection parameters quartz crystals are generally considered to be th e mainstay of frequency control components due to their low cost and ease of implementation. they are available from numerous vendors in many package types and with various specification options. all crystals used with intel ? ethernet controllers are described as ?at-cut?, which refers to the angle at which the unit is sliced with respect to the long axis of the quartz stone. table 5 lists the crystal electrical parameters and provides suggested values for typical designs. the parameters listed are described in the following subsections. table 5. crystal parameters parameter suggested value vibration mode fundamental nominal frequency 25,000 mhz at 25 c (required) frequency tolerance 30 ppm recommended; 50 ppm across the entire operating temperature range as required by ieee specifications 30 ppm required for the 82547GI(ei) temperature stability 50 ppm at 0 c to 70 c 30 ppm at 0 c to 70 c required for the 82547GI(ei) calibration mode parallel load capacitance 16 pf to 20 pf 18 pf required for the 82547GI(ei) shunt capacitance 6 pf maximum equivalent series resistance 50 ? maximum 10 ? maximum required for the 82547GI(ei) drive level 0.5 mw maximum aging 5 ppm per year maximum
82562ez(ex)/82547GI(ei) dual footprint design guide 8 . table 6 lists the approved crystals for use with the 83547gi(ei) b1 steppings. 3.1.1.1 vibration mode crystals in the frequency range listed in table 5 are available in both fundamental and third overtone. unless there is a special need for third overtone, use fundamental mode crystals. at any given operating frequency, third overtone crystals are thicker and more rugged than fundamental mode crystals. third overtone crystals are more suitable for use in military or harsh industrial environments. third overtone crystals require a trap circuit (extra capacitor and inductor) in the load circuitry to suppress fundamental mode oscillation as the circuit powers up. selecting values for these components is beyond the scope of this document. 3.1.1.2 nominal frequency intel? ethernet controllers use a crystal frequency of 25.000 mhz. the 25 mhz input is used to generate a 125 mhz transmit clock for 100base-tx and 1000base-tx operation; 10 mhz and 20 mhz transmit clocks, for 10base-t operation. 3.1.1.3 frequency tolerance the frequency tolerance for an ethernet physi cal layer device is dictated by the ieee 802.3 specification as 50 parts per million (ppm). this measurement is referenced to a standard temperature of 25 c. note: intel recommends a frequency tolerance of 30 ppm. 3.1.1.4 temperature stability and environmental requirements temperature stability is a standard measure of how the oscillation frequency varies over the full operational temperature range (and beyond). se veral optional temperature ranges are currently available, including -40 c to +85 c for industrial environments. some vendors separate operating temperatures from temperature stability. manufacturers may also list temperature stability as 50 ppm in their data sheets. note: crystals also carry other specifications for storage temperature, shock resistance, and reflow solder conditions. crystal vendors should be consulted early in the design cycle to discuss the application and its environmental requirements. 3.1.1.5 calibration mode the terms ?series-resonant? and ?parallel-resonant ? are often used to describe crystal circuits. specifying parallel mode is critical to determining how the crystal frequency is calibrated at the factory. table 6. 82547GI(ei) recommended crystals manufacturer manufacturer's part number raltron (<20 ? esr and +/-30 ppm) as-25.000-20-f-smd-tr txc 6c25000355
82562ez(ex)/82547GI(ei) dual footprint design guide 9 a crystal specified and tested as series resonant oscillates without problem in a parallel-resonant circuit, but the frequency is higher than nominal by several hundred parts per million. the purpose of adding load capacitors to a crystal circuit is to establish resonance at a frequency higher than the crystal?s inherent series resonant frequency. figure 4 illustrates a simplified schematic of the 82562ez(ex) and the 82547GI(ei) controller?s crystal circuit. the crystal and the capacitors form a feedback el ement for the internal inverting amplifier. this combination is called parallel-re sonant, because it has positive reactance at the selected frequency. in other words, the crystal behaves like an inductor in a parallel lc circuit. figure 4. crystal circuit 3.1.1.6 load capacitance the formula for crystal load capacitance is as follows: where c1 = c2 = 22 pf (as suggested in most intel reference designs) and c stray = allowance for additional capacitance in pads, traces and the chip carrier within the ethernet controller package an allowance of 3 pf to 7 pf accounts for lumped stray capacitance. the calculated load capacitance is 16 pf with an estimated stray capacitance of about 5 pf. individual stray capacitance components can be es timated and added. for example, surface mount pads for the load capacitors add approximately 2.5 pf in parallel to each capacitor. this technique is especially useful if y1, c1 and c2 must be pl aced farther than approximately one-half (0.5) inch from the controller. it is worth noting that thin circuit boards generally have higher stray capacitance than thick circuit boards. c1 c2 lan silicon x1 or xin lan silicon x2 or xout c l c 1 c 2 ? () c 1 c 2 + () ------------------------- c stray + =
82562ez(ex)/82547GI(ei) dual footprint design guide 10 standard capacitor loads used by crystal manufacturers include 16 pf, 18 pf and 20 pf. any of these values will generally operate with the contro ller. however, a difference of several picofarads between the calibrated load and the actual load will pull the oscillator slightly off frequency. note: c1 and c2 may vary by as much as 5% (approximately 1 pf) from their nominal values. 3.1.1.7 shunt capacitance the shunt capacitance parameter is relatively un important compared to load capacitance. shunt capacitance represents the effect of the crystal?s mechanical holder and contacts. the shunt capacitance should equal a maximum of 6 pf (7 pf is also acceptable). 3.1.1.8 equivalent series resistance equivalent series resistance (esr) is the real component of the crystal?s impedance at the calibration frequency, which the inverting amplifier?s loop gain must overcome. esr varies inversely with frequency for a given crystal family. the lower the esr, the fa ster the crystal starts up. use crystals with an esr value of 50 ? or better. note: check the specific controller documentation car efully; some devices may have tighter esr requirements. for example, intel recommends that 82547GI(ei) devices use crystals with an esr value of 10 ? or less. 3.1.1.9 drive level drive level refers to power dissipation in use. the allowable drive level for a surface mounted technology (smt) crystal is less than its through- hole counterpart, because surface mount crystals are typically made from narrow, rectangular at st rips, rather than circular at quartz blanks. some crystal data sheets list crystals with a maximum drive level of 1 mw. however, intel? ethernet controllers drive crystals to a level less than the suggested 0.5 mw value. this parameter does not have much value for on-chip oscillator use. 3.1.1.10 aging aging is a permanent change in frequency (and re sistance) occurring over time. this parameter is most important in its first year b ecause new crystals age faster than old crystals. use crystals with a maximum of 5 ppm per year aging. 3.1.2 reference crystal the normal tolerances of the discrete crystal co mponents can contribute to small frequency offsets with respect to the target center frequency. to minimize the risk of to lerance-caused frequency offsets causing a small percentage of production lin e units to be outside of the acceptable frequency range, it is important to account for those shifts while empirically determining the proper values for the discrete loading capacitors, c1 and c2. even with a perfect support circuit, most crystals will oscillate slightly higher or slightly lower than the exact center of the target frequency. therefor e, frequency measurements (which determine the correct value for c1 and c2) should be performe d with an ideal reference crystal. when the capacitive load is exactly equal to the crystal?s load rating, an ideal reference crystal will be perfectly centered at the desired target frequency.
82562ez(ex)/82547GI(ei) dual footprint design guide 11 3.1.3 reference crystal selection there are several methods available for ch oosing the appropriate reference crystal: if a saunders and associates (s&a) crystal network analyzer is available, then discrete crystal components can be tested until one is found with zero or nearly zero ppm deviation (with the appropriate capacitive load). a crystal with zero or near zero ppm deviation will be a good reference crystal to use in subsequent frequency tests to determine the best values for c1 and c2. if a crystal analyzer is not available, then the selection of a reference crystal can be done by measuring a statistically valid sample population of crystals, which has units from multiple lots and approved vendors. the crystal, which has an oscillation frequency closest to the center of the distribution, should be the reference crystal used during testing to determine the best values for c1 and c2. it may also be possible to ask the approved crystal vendors or manufacturers to provide a reference crystal with zero or nearly zero devi ation from the specified frequency when it has the specified cload capacitance. note: for 82547GI(ei) devices, intel? recommends choosing a crystal with a esr value of 10 ? or less, an equivalent cload of 18 pf, and a maximum of 30 ppm frequency shift. cload is defined to be the load capacitance of the crystal, specified by the crystal vendor. when choosing a crystal, customers must keep in mind that to comply with ieee specifications for 10/100 and 10/100/1000base-t ethernet lan, the tr ansmitter reference frequency must be precise within 50 ppm. intel? recommends customers to us e a transmitter reference frequency that is accurate to within 30 ppm to account for variations in crystal accuracy due to crystal manufacturing tolerance. for information about measuring transmitter reference frequency, refer to appendix a, ?measuring lan reference frequency using a frequency counter? . 3.1.4 circuit board since the dielectric layers of the circuit board are allowed some reasonable variation in thickness, the stray capacitance from the printed board (to the crystal circuit) will also vary. if the thickness tolerance for the outer layers of dielectric are co ntrolled within 17 percent of nominal, then the circuit board should not cause more than 2 pf va riation to the stray capacitance at the crystal. when tuning crystal frequency, it is recommended that at least three circuit boards are tested for frequency. these boards should be from different production lots of bare circuit boards. alternatively, a larger sample population of circuit boards can be used. a larger population will increase the probability of obtaining the full range of possible variations in dielectric thickness and the full range of variation in stray capacitance. next, the exact same crystal and discrete load capacitors (c1 and c2) must be soldered onto each board, and the lan reference frequency should be measured on each circuit board. the circuit board, which has a lan reference frequency closest to the center of the frequency distribution, should be used while performing the frequency measurements to select the appropriate value for c1 and c2. 3.1.5 temperature changes temperature changes can cause the crystal frequency to shift. therefore, frequency measurements should be done in the final system chassis acros s the system?s rated operating temperature range.
82562ez(ex)/82547GI(ei) dual footprint design guide 12 3.1.6 integrated magnetics module the magnetics module has a critical effect on overall ieee and regulatory conformance. the device should meet the performance required for a design with reasonable margin to allow for manufacturing variation. occasionally, components that meet basic specifications may cause the system to fail ieee testing because of interactio ns with other components or the printed circuit board itself. carefully qualifying new magnetics modules can go a long way toward preventing this type of problem. the steps involved in magnetics module qualif ication are similar to those for oscillator qualification: 1. verify that the vendor's published specifications in the component datash eet meet the required ieee specifications. 2. independently measure the component's electri cal parameters on the test bench, checking samples from multiple lots. check that the measured behavior is consistent from sample to sample as well as meeting the published specifications. 3. perform physical layer conformance testing and emc (fcc and en) testing in real systems. vary temperature and voltage while perfor ming system level tests (for ieee only). magnetics modules for 1000base-t ethernet are similar to those designed solely for 10/100 mbps, with the exception of four differential signal pairs instead of two for 10/100 mbps. 3.2 designing with the 82562ez( ex) platform lan connect device this section provides design guidelines specific to the plc device. 3.2.1 82562ez/ex plc device lan disable guidelines note: ichx integrated lan controller resides on the ichx vccsus3_3 and vccsus1_8 power wells (typically referred to as ?auxiliary? (?aux?) or ?standby? supplies at the platform level). the ichx integrated lan?s rst# is the ichx resume-well input. it can be held low indefinitely to keep the ichx integrated lan controller in a reset state. the lan reset (rst#) signal must not be deasserted sooner than 10 ms after th e resume power supply reaches its nominal voltage. this ensures that the ichx integrated lan controller is initialized. figure 5 illustrates a possible solution for ichx integrated lan disable.
82562ez(ex)/82547GI(ei) dual footprint design guide 13 figure 5. lan disable circuitry note: the 100 ? resistors for the test mode signals are required for the exclusive or (xor) tree and isolate mode. 3.2.2 serial eeprom for 82562ez(ex) implementations serial eeprom for lan implementations based on 82562ez(ex) devices connects to the ich5. depending upon the size of the eeprom, the 82562ez(ex) may or may not support legacy manageability. table 7 and table 8 list the eeprom map for the 82562ez(ex) plc device. for details on the eeprom, refer to the appropriate i/o control hub 2, 3, 4, 5, 6, and 7 eeprom map and programming information . note: no manageability provided. 470 ? 3.3vstb 1k mmbt3904 lan_rst# ichx rsmrst# sensor/ supervisor rst# 3.3vstb 1k 3.3vstb super io gp port or ichx gpio 24, 25, 27, 28 or controller (mobile) testen isol_tck isol_ti isol_tex 100 ? 100 ? 100 ? 100 ? table 7. 82562ez(ex) memory layout (128 byte eeprom) 00h 3fh hw/sw reserved area
82562ez(ex)/82547GI(ei) dual footprint design guide 14 note: legacy manageability only. 3.2.3 magnetics modules fo r 82562ez(ex) plc device a 5-core magnetics module should be carefully selected for your design. table 9 lists suggested integrated magnetics modules for use with th e 82562ez(ex) plc device. these modules also contain integrated usb jacks. note: these components are pin-compatible wi th the magnetics modules listed in table 13 for the 82547GI(ei) controller. 3.2.4 power supplies for 82562ez(ex) plc implementations the 82562ez(ex) plc device uses a single 3.3 v power supply. the 3.3 v supply must provide approximately 90 ma current for full speed operation. standby power must be furnished in order to wake up from powerdown. 3.2.5 82562ez(ex) devi ce test capability the device contains an xor test tree mechanism fo r simple board tests. details of the xor tree operation are contained in the 82562et lan on motherboard design guide . 3.3 designing with the 82547GI(ei) gigabit ethernet controller this section provides design guidelines specific to the 82547GI(ei) controller. 3.3.1 82547GI(ei) ethernet controller lan disable guidelines the 82547GI(ei) controller has a lan_disable# function that is present on flsh_so ball p9. this pin can be connected to a gpio pin on the ich5 component to allow the bios to disable the ethernet port (see figure 6 ). if the serial flash interface is populated, make sure the flash serial output pin does not interfere with this function. table 8. 82562ez(ex) memory layout (512 byte eeprom) 00h 3fh hw/sw reserved area 40h ffh asf and legacy manageability table 9. 82562ez(ex) recommended magnetics modules manufacturer manufacturer's part number pulse jw0a1p01r-e stewart si-70027 foxconn ubc11123-j51
82562ez(ex)/82547GI(ei) dual footprint design guide 15 for best results, do not attempt to use the lan_power_good signal for a lan disable input. this pin is intended to operate as a power- on reset connected to a power monitor circuit. the input of flsh_so (ball p9) is the lan_disable signal. it is sampled on the rising edge of lan_pwr_good and/or rst#. the signal must be held valid for 80 ns after either rising edge. if sampled high, the lan functions normally. if sampled low, then the following occurs: 1. the lan is disabled. 2. the phy is powered down. 3. most mac clock domains are gated. 4. most functional blocks are held in reset. 5. the device is in a low power state ? equivalent to d3 w/ no wake or manageability. note: to use this configuration for the 82562ez(ex) platform lan connect device, be sure the and gate u1 is populated. depopulate the 0 ? resistor r2. figure 6. 82547GI(ei) lan disable circuitry 3.3.2 serial eeprom for 82547GI(ei) controller implementations the 82547GI(ei) gigabit ethernet controller can use either a microwire* or an spi* serial eeprom. the eeprom mode is selected on the eemode input (ball c4). a pull-up resistor to vcc denotes spi*. a pull-down resistor to ground denotes microwire. several words of the eeprom are accessed automatically by the device af ter reset to provide pre-boot configuration data before it is accessed by host software. the remainder of the eeprom space is available to software for storing the mac address, serial numbers, and additional information. io control hub 5 super io chip 82547GI(ei) rst# rst# (b9) rsm_rst# r1 10 k r2 0 ohm pop = y lan_pwr_good (a9) 82562ez(ex) disable circuit u1 flsh_so (p9) pop = y means populate this option
82562ez(ex)/82547GI(ei) dual footprint design guide 16 for non-asf applications, use a 64 register by 16-bit microwire serial eeprom. for asf 1.0 applications, use larger 93c66 microwire or at25040 spi* serial eeprom. asf 2.0 requires an 8k spi* serial eeprom. intel has an ms-dos* software utility called eeupdate, which can be used to program eeprom images in development or production line environments. to obtain a copy of this program, contact your intel representative. the eeprom access algorithm programmed into the 82547GI(ei) controller is compatible with most, but not all, commercially available 3.3 v microwire interface, serial eeprom devices, with 64 x 16 (or 256 x 16) organization and a 1 mhz speed rating. the 82547GI(ei)'s eeprom access algorithm drives extra pulses on the shift clock at the beginnings and ends of read and write cycles. the extra pulses may violate the timing specifica tions of some eeprom devices. in selecting a serial eeprom, choose a device that specifies ?don't care? shift clock states between accesses. microwire eeproms that have been found to work satisfactorily with the 82547GI(ei) gigabit ethernet controller are listed in the following table: spi* eeproms that have been found to work satisfactorily with the 82547GI(ei) device are listed in table 11 . spi eeproms must be rated for a clock rate of at least 2 mhz. table 10. microwire 64 x 16 serial eeproms manufacturer manufacturer's part number atmel at93c46 catalyst cat93c46 1 1. revision h is not supported. product die revision letter is marked on top of the package as a suffix to the production data code (e.g., ayww h .) table 11. spi serial eeproms for 82547GI(ei) controller application manufacturer manufacturer's part number asf 1.0 or ipmi pass through atmel at25040 asf 2.0 or ipmi advanced pass through atmel at25080
82562ez(ex)/82547GI(ei) dual footprint design guide 17 3.3.3 eeprom map information table 12 summarizes the eeprom map for the 82547GI(ei) gigabit ethernet controller. table 12. 82547GI(ei) eeprom memory layout note: full manageability provided. 3.3.4 magnetics modules for 82547GI(ei) controller applications carefully select a gigabit magnetics module for your design. table 13 lists suggested integrated magnetics modules for use with the 82547GI(ei) device. these modules also contain integrated usb jacks. a good quality gigabit ethernet cont roller can also be used with the 82562ez(ex) plc device. note: these components are pin-compatible with the magnetics modules shown in table 9 for the 82562ez(ex) platform lan connect device. 3.3.5 power supplies for the 82547GI(ei) device the 82547GI(ei) controller requires three power supplies. the 1.2 v supply must provide approximately 550 ma current. the 1.8 v supply must provide approximately 230 ma current. the 3.3 v supply must provide only 5 ma current. a central power supply can provide all the requir ed voltage sources, or the power can be derived and regulated locally near the ethernet control circu itry. keep in mind that all voltage sources must remain present during powerdown in order to use the 82547GI(ei) ethernet controller's lan wake up capability. this consideration makes it more likely that at least some of the voltage sources will be local. 00h 3fh hw/sw reserved area 40h ffh asf and legacy manageability 100h 19f manageability packet filter data 1a0 ... eeprom end loadable manageability firmware code table 13. 82547GI(ei) recommended magnetics modules manufacturer manufacturer's part number pulse jw0a2p019d others tbd
82562ez(ex)/82547GI(ei) dual footprint design guide 18 instead of using external regulators to supply 1.2 v and 1.8 v, the designer can use power transistors in conjunction with on-chip regulation circuitry. see the reference schematic for an implementation example. the 82547GI(ei) controller has a lan_pwr_good inpu t. treat this signal as an external device reset which works in conjunction with the internal power-on reset circuitry. in the situation where a central power supply furnishes all the voltage sources, lan_pwr_good can possibly be tied to the power_good output of the power supply. designs that generate some of the voltages locally can connect lan_pwr_good to a power mo nitor chip. ensure that the system drives lan_pwr_good inactive for at least 80 ms after power-up. the power sources are all expected to ramp up during a brief power-up interval (approximately 20 ms.) with lan_pwr_good de-asserted. do not leave the 82547GI(ei) controller in a prolonged state where some, but not all, voltages are applied. 3.3.6 82547GI(ei) controller power supply filtering provide several bypass capacitors for each power rail, selecting values in the range of 0.01 f to 0.01 f. if possible, orient the capacitors clos e to the device and adjacent to power pads. decoupling capacitors should connect to the power planes with short, thick (15 mils - 0.4mm or more) traces and 14 mil (0.35 mm) vias. furnish approximately 20 f of bulk capacitance for each of the main 1.2 v and 1.8 v levels. a convenient way to do this is to use about two 10 f capacitors, placing them as close to the device power connections as possible. 3.3.7 82547GI(ei) controller powe r management and wake up the 82547GI(ei) gigabit ethernet controller supports low power operation as defined in the pci bus power management specification. there are two defined power states, d0 and d3. the d0 state provides full power operation and is divided into two sub-states: d0u (uninitialized) and d0a (active). the d3 state provides low power operation and is also divided into two sub-states: d3hot and d3cold. to enter the low power state, the software driver must stop data transmission and reception. either the operating system or the driver must program the power management control/status register (pmcsr) and the wakeup control register (wuc). if wakeup is desired, the appropriate wakeup lan address filters must also be set. the initial power management settings are specified by eeprom bits. when the 82547GI(ei) controller transitions to eith er of the d3 low power states, the 1.2 v, 1.8 v, and 3.3 v sources must continue to be supplied to the device. otherwise, it will not be possible to use a wakeup mechanism. the aux_power signal is a logic input to the 82547GI(ei) controller that denotes auxiliary power is available. if aux_power is asserted, the 82547GI(ei) device will advertise that it supports wake up from a d3cold state. the 82547GI(ei) device supports both advanced power management (apm) wakeup and advanced configuration and power interface (acp i) wakeup. apm wakeup has also been known in the past as ?wake on lan?. wakeup uses the pme# signal to wake the system up. pme# is an active low signal connected to a gpio port on the ich5 that goes active in re sponse to receiving a ?magic packet?, a network wakeup packet, or link status change indication. pme# remains asserted until it is disabled through the power management control/status register.
82562ez(ex)/82547GI(ei) dual footprint design guide 19 3.3.8 82547GI(ei) device test capability the 82547GI(ei) gigabit ethernet controller contains a test access port conforming to the ieee 1149.1a-1994 (jtag) boundary scan specification. to use the test access port, connect these balls to pads accessible by your test equipment. be sure to connect the trst# input to ground through a pull-down resistor (approximately 1k value) so that the test capability cannot be invoked by mistake. a bsdl (boundary scan definition language) file describing the 82547GI(ei) device is available for use in your test environment. the controller also contains an xor test tree mechanism for simple board tests. details of xor tree operation may be obtained through your intel representative.
82562ez(ex)/82547GI(ei) dual footprint design guide 20 note: this page intentionally left blank.
82562ez(ex)/82547GI(ei) dual footprint design guide 21 4.0 ethernet component layout guidelines these sections provide recommendations for performing printed circuit board layouts. good layout practices are essential to meet ieee phy co nformance specifications and emi regulatory requirements. 4.1 general layout considerations for ethernet controllers critical signal traces should be kept as short as possible to decrease the likelihood of being affected by high frequency noise from other signals, including noise carried on power and ground planes. keeping the traces as short as possible can also reduce capacitive loading. since the transmission line medium extends onto the printed circuit board, special attention must be paid to layout and routing of the differential signal pairs. designing for gigabit operation is very similar to designing for 10 and 100 mbps. for the 82547GI(ei) gigabit ethernet controller, system level tests should be performed at all three speeds. 4.1.1 guidelines for component placement component placement can affect signal quality, emissions, and component operating temperature. this section provides guide lines for component placement. careful component placement can: decrease potential problems directly related to electromagnetic interference (emi), which could cause failure to meet applicab le government test specifications. simplify the task of routing traces. to some extent, component orientation will affect the complexity of trace routing. the overall objective is to minimize turns and crossovers between traces. minimizing the amount of space needed for the et hernet lan interface is important because other interfaces will compete for physical space on a motherboard near the connector. the ethernet lan circuits need to be as close as possible to the connector (see figure 5 ).
82562ez(ex)/82547GI(ei) dual footprint design guide 22 figure 5. general placement distances figure 5 shows some basic placement distance guidelines. the figure shows two differential pairs, but can be generalized for a gigabit system with four analog pairs. the ideal placement for the ethernet silicon would be approximately one inch behind the magnetics module. while it is generally a good idea to minimize lengths and distances, this figure also illustrates the need to keep the lan silicon away from the edge of the board and the magnetics module for best emi performance. 4.1.2 crystals crystals should not be placed near i/o ports or board edges. radiation from these devices may be coupled onto the i/o ports or out of the system chassis. crystals should also be kept away from the ethernet magnetics module to prevent interference. traces should be referenced to a continuous low impedance plane. place the crystal and load capacito rs on the printed circuit boards as close to the ethernet component as possible, within 0.75 inch. keep ot her potentially noisy traces away from the crystal traces. 4.1.3 board stack up recommendations printed circuit boards for these designs typically have four, six, eight, or more layers. here is a description of a typical six-layer board stackup: layer 1 is a signal layer. it can contain the diffe rential analog pairs from the ethernet device to the magnetics module. layer 2 is a signal ground layer. chassis ground may also be fabricated in layer 2 under the connector side of the magnetics module. lan silicon integrated rj-45 w/lan magnetics keep lan silicon 1 to 4 inches from lan connector keep 100 mil minimum distance between tx and rx traces (300 mils is preferred) keep silicon traces at least 1 inch from edge of pcb (2 inches preferred)
82562ez(ex)/82547GI(ei) dual footprint design guide 23 layer 3 is used for power planes. layer 4 is a signal layer. for gigabit designs, it is common to route two of the differential pairs on this layer. this board stack up configuratio n can be adjusted to conform to your company's design rules. 4.1.4 differential pa ir trace routing trace routing considerations are important to minimize the effects of crosstalk and propagation delays on sections of the board where high-speed signals exist. signal traces should be kept as short as possible to decrease interference from other si gnals, including those propagated through power and ground planes. observe the following suggestions to help optimize board performance: maintain constant symmetry and spacing betw een the traces within a differential pair. keep the signal trace lengths of a di fferential pair equal to each other. keep the total length of each di fferential pair under four inches. designs with differential traces longer than 5 inches are much more lik ely to have degraded receive bit error rate (ber) performance, ieee phy conformance failures, and/or excessive electromagnetic interference (emi) radiation do not route the transmit differ ential traces closer than 100 mi ls to the receive differential traces. do not route any other signal traces both paralle l to the differential traces , and closer than 100 mils to the differential traces (300 mils is recommended). keep maximum separation within differential pairs to seven mils. for high-speed signals, the number of corners and vias should be kept to a minimum. if a 90 bend is required, it is recommended to use two 45 bends instead. see figure 6 . traces should be routed away from board ed ges by a distance greater than the trace height above the ground plane. this allows the fiel d around the trace to couple more easily to the ground plane rather than to adjacent wires or boards. do not route traces and vias under crystals or oscillators. this will prevent coupling to or from the clock. and as a general rule, place traces fr om clocks and drives at a minimum distance from apertures by a distance that is great er than the largest aperture dimension. figure 6. trace routing 45 45
82562ez(ex)/82547GI(ei) dual footprint design guide 24 the reference plane for the differential pairs sh ould be continuous and low impedance. it is recommended that the reference plane be either ground or 1.8 v (the voltage used by the phy). this provides an adequate return pa th for and high frequency noise currents. do not route differential pairs over splits in the associated reference plane. differential termination components should be pl aced as close as possible to the lan silicon. 4.1.5 signal trace geometry the key factors in controlling trace emi radiation are the trace length and the ratio of trace-width to trace-height above the ground plane. to mi nimize trace inductance, high-speed signals and signal layers that are close to a ground or power plane should be as short and wide as practical. ideally, this trace width to height above the ground plane ratio is between 1:1 and 3:1. to maintain trace impedance, the width of the trace should be modified when changing from one board layer to another if the two layers are not equidistant from the power or ground plane. each pair of signal should have a differential impedance of 100 ? . +/- 20%. if a particular tool cannot design differential traces, it is permissible to specify 55-65 ? single-ended traces as long as the spacing between the two traces is minimized. as an example, consider a differential trace pair on layer 1 that is eight mils (0.2 mm) wide and two mils (0.05 mm) thick, with a spacing of eight mils (0.2mm). if the fiberglass layer is eight mils (0.2 mm) thick with a dielectric constant, e r , of 4.7, the calculated single-ended impedance would be approximately 61 ? and the calculated differential impedance would be approximately 100 ? . when performing a board layout, do not allow th e cad tool auto-router to route the differential pairs without intervention. in most cases, the differential pairs will have to be routed manually. the components should be laid out in the following order of priority: 1. differential traces 2. termination resistors 3. bypass capacitors 4. other components this allows placing those components in the best locations and avoids using critical space by non- critical components. note: measuring trace impedance for layout designs targeting 100 ? often results in lower actual impedance. designers should verify actual trace impedance and adjust the layout accordingly. if the actual impedance is consistently low, a target of 105 to 110 ? should compensate for second order effects. it is necessary to compensate for trace-to-trace edge coupling, which can lower the differential impedance by up to 10 ? , when the traces within a pair are closer than 30 mils (edge to edge). 4.1.6 trace length and symmetry as indicated earlier in section 4.1.4 , the overall length of differential pairs should be less than four inches measured from the ethernet device to the magnetics. the differential traces should be equal within 50 mils (1.25 mm) within each pair and as symmetrical as possible. asymmetrical and un equal length traces in the differential pairs contribute to common mode noise. common mo de noise can degrade the receive circuit?s performance and contribute to radiated emissions.
82562ez(ex)/82547GI(ei) dual footprint design guide 25 4.1.7 impedance discontinuities impedance discontinuities cause unwanted signal reflections. avoid vias (signal through holes) and other transmission line irregularities. if vias must be used, a reasonable budget is two per differential trace. unused pads and stub traces should also be avoided. 4.1.8 reducing circuit inductance traces should be routed over a continuous groun d plane with no interruptions. if there are vacant areas on a ground or power plane, the signal c onductors should not cros s the vacant area. this increases inductance and associated radiated noise levels. noisy logic grounds should be separated from analog signal grounds to reduce coupling. noisy logic grounds can sometimes affect sensitive dc subsystems such as analog to digital conversion, operational amplifiers, etc. all ground vias should be connected to every ground plane; and si milarly, every power via, to all power planes at equal potential. this helps reduce circuit inducta nce. another recommendation is to physically locate grounds to minimize the loop area between a signal path and its return path. rise and fall times should be as slow as possible. because signals with fast rise and fall times contain many high frequency harmonics, which can radiate significantly. the most sensitive signal returns closest to the chassis ground should be connected together. this will result in a smaller loop area and reduce the likelihood of crosstalk. the effect of differen t configurations on the amount of crosstalk can be studied using electronics modeling software. 4.1.9 signal isolation to maintain best signal integrity, keep digital signals far away from the analog traces. a good rule of thumb is no digital signal should be within 300 mils (7.5 mm) of the differential pairs. if digital signals on other board layers cannot be separated by a ground plane, they should be routed at right angles with respect to the differential pairs. if there is another lan controller on the board, take care to keep the differential pa irs from that circuit away. some rules to follow for signal isolation: separate and group signals by function on separate layers if possible. maintain a gap of 100 mils between all differential pairs (ethernet) an d other nets, but group associated differential pairs together. note: over the length of the trace run, each differential pair should be at least 0.3 inches away from any parallel signal traces. physically group together all components as sociated with one clock trace to reduce trace length and radiation. isolate i/o signals from high-speed signals to minimize crosstalk, which can increase emi emission and susceptibility to emi from other signals. avoid routing high-speed lan traces near othe r high-frequency signals associated with a video controller, cache controller, processor, or other similar devices. 4.1.10 power and ground planes good grounding requires minimizing inductance levels in the interconnections and keeping ground returns short, signal loop areas small, and power inputs bypassed to signal return, will significantly reduce emi radiation.
82562ez(ex)/82547GI(ei) dual footprint design guide 26 the following guidelines help reduce circuit induc tance in both backplanes and motherboards: route traces over a continuous plane with no interruptions. do not route over a split power or ground plane. if there are vacant areas on a gr ound or power plane, avoi d routing signals over the vacant area. this will increase inductance and emi radiation levels. separate noisy digital grounds from analog grounds to reduce coupling. noisy digital grounds may affect sensitive dc subsystems. all ground vias should be connected to every ground plane; and every power via should be connected to all power planes at equal potential. this helps reduce circuit inductance. physically locate grounds between a signal path and its return. this will minimize the loop area. avoid fast rise/fall times as much as possible. signals with fast rise and fall times contain many high frequency harmonics, which can radiate emi. the ground plane beneath the magnetics module should be split. the rj-45 connector side of the transformer module should have chassis ground beneath it. split ground planes for magnetics modules 4.1.11 traces for decoupling capacitors traces between decoupling and i/o filter capacitors should be as short and wide as practical. long and thin traces are more inductive and would reduce the intended effect of decoupling capacitors. also for similar reasons, traces to i/o signals and signal terminations should be as short as possible. vias to the decoupling capacitors should be sufficiently large in diameter to decrease series inductance. 4.1.12 ground planes unde r the magnetics module the magnetics module chassis or output ground (secondary side of transformer) should be separated from the digital or input ground (primary side) by a physical separation of 100 mils minimum. splitting the ground planes beneath the transformer minimizes noise coupling between the primary and secondary sides of the transformer and between the adjacent coils in the magnetics. this arrangement also improves the common mode choke functionality of magnetics module. table 7 illustrates the split plane layout for a discrete magnetics module. capacitors are used to interconnect chassis ground and signal ground. . figure 7. ground plane separation magnetics module ground plane void or separate 0.10 inches minimum spacing separate chassis ground plane gnd_plane_sep
82562ez(ex)/82547GI(ei) dual footprint design guide 27 figure 8 below shows the preferred method for implementing a ground split under an integrated magnetics module/rj-45 connector. the capacitor stuffing options (c1 ? c6) are used to reduce/ filter high frequency emissions. the value(s) of the capacitor stuffing options may be different for each board. experiments will need to be performed to determine which value(s) provide best emi performance. figure 8. ideal ground split implementation the table below gives some star ting values for these capacitors. the placement of c1 ? c6 may also be different for each board design (i.e., not all of the capacitors may need to be populated). also, the capacitors may not be needed on both sides of the magnetic module. board edge rj/mag. chassis gnd rj shield connected to chassis gnd capacitor stuffing options capacitor stuffing options resistive terminations digital gnd c1 c2 c3 c4 c5 c6 capacitors value c3, c4 4.7 f or 10 f c1, c2, c5, c6 470 pf to 0.1 f
82562ez(ex)/82547GI(ei) dual footprint design guide 28 4.1.13 special considerations for n on-integrated magne tics modules and rj-45 connectors it is possible to employ discrete (non-integrated) magnetics modules and rj-45 connectors. similar rules will apply to design and layout. the differential pairs should be routed to be as short and symmetrical as possible and the overall lengths of the differential pairs (including the width of the magnetics module) should not exceed approximately four inches. additional design and layout steps will be required to add a dedicated board termination plane parallel to chassis ground, 75 ? termination resistors, and a 1500 pf capacitor. this ?bob smith? termination scheme is normally contained inside an integrated magnetics module. in ethernet designs, it is common practice to terminate unused connections on the rj-45 connector and the magnetics module to ground. depending on overall shielding and grounding design, this may be done to the chassis ground, signal ground, or a termination plane. care must be taken when using various grounding methods to insure that emission requirements are met. in the ?bob smith? termination method, a floating termination plane is cut out of a power plane layer. this floating plane acts as a plate of a capacitor with an ad jacent ground plane. the signals can be routed through 75 ? resistors to the plane. stray energy on unused pins is then carried to the plane. it is recommended that the term ination plane capacitance equal a minimum value of 1500 pf. this helps reduce the amount of crosstalk on the differential pairs from the unused pairs of the rj-45 connector. pads may be placed for an additional capacitance to chassis ground, which may be required if the termination plan e capacitance is not large enough to pass eft (electrical fast transient) testing. if a discrete capacitor is used , to meet the eft requirements it should be rated for at least 1000 vac. figure 9. termination plane example for 82562ez(ex) plc device and discrete magnetics n/c rj-45 magnetics module rdp rdn tdp tdn termination plane additional capacitance that may be required for eft testing lan_term_plane
82562ez(ex)/82547GI(ei) dual footprint design guide 29 4.2 layout for the 82562ez(ex) platform lan connect device this section provides layout guidelines specific to the 82562ez(ex) plc device. 4.2.1 termination resistors for de signs based on 82 562ez(ex) plc device two differential pairs are terminated using 54.9 ? (1% tolerance) resistor s, placed near the lan controller. one resistor connects to the mdi+ (mdi positive) signal trace and another resistor connects to the mdi- (mdi negative) signal trace (see figure 10 ). termination resistor values we re recently increased from 49.9 ? to 54.9 ? to improve return loss. however, on some designs, this change caused the pcb?s output amplitude to be slightly above the peak-to-peak center of the ieee specification. as a result, rbias resistor values were increased (rbias10 549 to 619 ? and rbias100 619 to 649 ? ) to reduce the pcb?s output amplitude to better meet the ieee peak-to-peak center specification. for 100base-tx designs, the ieee specification allows a -950 mvpk to -1050 mvpk for the negative peak and +950 mvpk to +1050 mvpk fo r the positive peak. ideally, a typical pcb output amplitude should be within -975 mvpk to -1025 mvpk for the negative peak and +975 mvpk to +1025 mvpk for the positive peak. for 10base-t designs, the ieee specification allows a -2.2 mvpk to -2.8 mvpk for the negative peak and +2.2 mvpk to +2.8 mvpk for the positi ve peak. ideally, a typical pcb output amplitude should be within -2.35 mvpk to -2.55 mvpk for the negative peak and +2.35 mvpk to +2.55 mvpk for the positive peak. the rbias values previously listed should be c onsidered starting values. intel recommends that board designers measure each of their pcb?s output amplitude and then adjust the rbias values as required. figure 10. 82562ez(ex) plc device differential signal termination 4.2.2 light emitting diodes for desi gns based on 82562ez(ex) plc device the 82562ez(ex) plc device has three high-current outputs to directly drive leds for link, activity and speed indication. since leds are likely to be integral to a magnetics module, take care to route the led traces away from potential sour ces of emi noise. in some cases, it may be desirable to attach filter capacitors. intel lan device magnetics module rj4 5 lan connect interface intel ich5 ? place termination resistors as close to the intel lan device as possible.
82562ez(ex)/82547GI(ei) dual footprint design guide 30 4.3 layout for the 82547GI(ei) gigabit ethernet controller 4.3.1 termination resistors for designs based on 82547GI(ei) gigabit ethernet controller the four differential pairs are terminated with 49.9 ? (1% tolerance) resistors, placed near the 82547GI(ei) controller. one resistor connects to the mdi+ signal trace and another resistor connects to the mdi- signal trace. the opposite en ds of the resistors connect together and to ground through a single 0.1 f capacitor. the capacitor should be placed as close as possible to the 49.9 ? resistors, using a wide trace. do not vary the suggested component values. be sure to lay out symmetrical pads and traces for these components such that the length and symmet ry of the differential pairs are not disturbed. 4.3.2 light emitting diode s for designs based on 82547GI(ei) controller the 82547GI(ei) controller provides four programmable high-current outputs to directly drive leds for link activity and speed indication. since th e leds are likely to be integral to a magnetics module, take care with care to route the led traces away from potential sources of emi noise. in some cases, it may be desirable to attach filter capacitors. 4.4 physical layer conformance testing physical layer conformance testing (also known as ieee testing) is a fundamental capability for all companies with ethernet lan products. phy testing is the final determination that a layout has been performed successfully. if your company does not have the resources and equipment to perform these tests, consider contracting the tests to an outside facility. crucial tests are as follows, listed in priority order: bit error rate (ber). good indicator of real world network performance. perform bit error rate testing with long and short cables and many link partners. the test limit is 10-11 errors. output amplitude, rise and fall time (10/100 mbps), symmetry and droop (1000 mbps). for the 82547GI(ei) controller, use the appropriate phy test waveform. return loss. indicator of proper impedance matching, measured through the rj-45 connector back toward the magnetics module. jitter test (10/100 mbps) or unfiltered jitter test (1000 mbps). indicator of clock recovery ability (master and slave for gigabit controller).
82562ez(ex)/82547GI(ei) dual footprint design guide 31 4.5 troubleshooting common physical layout issues the following is a list of common physical layer design and layout mistakes in lan on motherboard designs. 1. unequal length of the two traces within a differential pair. inequalities create common-mode noise and will distort the transmit or receive waveforms. 2. lack of symmetry between the two traces w ithin a differential pair . asymmetry can create common-mode noise and distort the waveforms. for each component and/or via that one trace encounters, the other trace should encounter the same component or a via at the same distance from the ethernet silicon. 3. excessive distance between the ethernet silicon and the magnetics. long traces on fr4 fiberglass epoxy substrate will attenuate the analog signals. in addition, any impedance mismatch in the traces will be aggravated if they are longer than the four inch rule. 4. routing any other trace parallel to and close to one of the differential traces. crosstalk getting onto the receive channel will cause degraded long cable ber. crosstalk getting onto the transmit channel can cause exces sive emi emissions and can cause poor transmit ber on long cables. at a minimum, other signals should be kept 0.3 inches from the differential traces. 5. routing one pair of differential traces too clos e to another pair of differential traces. after exiting the ethernet silicon, the trace pairs should be kept 0.3 inches or more away from the other trace pairs. the only possible exceptions are in the vicinities where the traces enter or exit the magnetics, the rj-45 conn ector, and the ethernet silicon. 6. use of a low quality magnetics module. 7. re-use of an out-of-date physical layer schematic in a ethernet silicon design. the terminations and decoupling can be different from one phy to another. 8. incorrect differential trace impedances. it is important to have ~100 ? impedance between the two traces within a differential pair. this becomes even more important as the differential traces become longer. to calculate differential impedance, many impedance calculators only multiply the single-ended impedance by two. this does not take into account edge-to-edge capacitive coupling between the two traces. when the two traces within a differential pair are kept close to each other, the edge coupling can lower the effective differential impedance by 5 ? to 20 ? . short traces will have fewer problems if the differential impedance is slightly off target. 9. for 82562ez(ex) plc designs, use of capacitor that is too large between the transmit traces and/or too much capacitance on the magnetic module's transmit center tap to ground. using capacitors more than a few pf in either of these locations can slow the 100 mbps rise and fall time. this will also cause return loss to fail at higher frequencies and will degrade the transmit ber performance. if a capacitor is used, it shou ld almost certainly be less than 22 pf.
82562ez(ex)/82547GI(ei) dual footprint design guide 32 note: this page intentionally left blank.
82562ez(ex)/82547GI(ei) dual footprint design guide 33 5.0 design and layout checklists the design and layout checklists are in portable da ta format (pdf) and available to aid designers via: http://developer.intel.com.
82562ez(ex)/82547GI(ei) dual footprint design guide 34 note: this page intentionally left blank.
82562ez(ex)/82547GI(ei) dual footprint design guide 35 6.0 ball number to signal mapping with population options table 14 lists the ball names for both devices corresponding to the shared ball number. please note that signal names may vary slightly from the names on the reference schematic in section 7.0 . the schematic names follow conventions used by intel design engineers on their design tools. table 14. ball number to signal mapping (sheet 1 of 7) b a l l ref 82562ez(ex) pin name 82547GI(ei) pin name signal name difference? 82562ez(ex) connection? pop option required? comment a1 nc nc a2 nc nc x a3 3.3 v 3.3 v x a4 nc nc x a5 nc nc x a6 nc pme# x a7 3.3 v 3.3 v x a8 nc nc x a9 nc lan_pwr_good x a10 nc smbclk x a11 vcct 3.3 v x a12 liled# led0/link_up# x x x same signal different name a13 testen test x x x same signal different name a14 nc nc b1 nc nc x b2 nc nc x b3 vss vss x b4 nc nc x b5 nc nc x b6 nc nc x b7 vss vss x b8 nc nc x b9 nc rst# x b10 nc smb_alert# x
82562ez(ex)/82547GI(ei) dual footprint design guide 36 b11 spdled# led2/link100# x x x same signal different name b12 tout led3/link1000# x x x 82562ez: nc 82547GI(ei): led b13 rbias100 ctrl18 x x x 82562ez: 649 ohm external pull-down 82547GI(ei): voltage transistor connection b14 rbias10 ieee_test+ x x x 82562ez: 619 ohm external pull-down 82547GI(ei): ieee phy te st c1 nc nc x c2 nc nc x c3 nc nc x c4 nc eemode x c5 nc nc x c6 nc nc x c7 nc nc x c8 nc nc x c9 nc smbdata x c10 vss vss x c11 actled# led/activity# x x x same signal different name c12 vss analog_vss x c13 tdp mdi[0]+ x x x connected to magnetics. c14 tdn mdi[0]- x x x connected to magnetics. d1 nc nc x d2 nc nc x d3 nc nc x d4 vss vss x x x connected to vss d5 vss vss x d6 vss vss x x x connected to vss d7 vss vss x d8 vss vss x d9 nc nc x table 14. ball number to signal mapping (sheet 2 of 7) (continued) b a l l ref 82562ez(ex) pin name 82547GI(ei) pin name signal name difference? 82562ez(ex) connection? pop option required? comment
82562ez(ex)/82547GI(ei) dual footprint design guide 37 d10 isol_exec nc x x x 82562ez: no connect. internal pull-down. 82547GI(ei): no connect. d11 nc 1.8 v x d12 isol_ti 1.8 v x x x 82562ez: no connect. internal pull-down. 82547GI(ei): 1.8 v. d13 vssa analog_vss x d14 isol_tck ieee_test- x x x 82562ez: no connect. internal pull-down. 82547GI(ei): ieee phy te s t . e1 vcc 3.3 v x e2 vss vss x e3 nc nc x e4 vss vss x x x connected to vss e5 vss vss x e6 vss vss x e7 vss vss x e8 vss vss x e9 vss vss x e10 vss vss x x x connected to vss e11 vcct analog_1.2v x x x 3.3 v / 1.2 v plane e12 vcct analog_1.2v x x x 3.3 v / 1.2 v plane e13 rdp mdi[1]+ x x x connected to magnetics. e14 rdn mdi[1]- x x x connected to magnetics. f1 nc nc x f2 nc nc x f3 nc nc x f4 vss vss x f5 vss vss x x x connected to vss f6 vss vss x f7 vss vss x f8 vss vss x f9 vss vss x f10 vss vss x table 14. ball number to signal mapping (sheet 3 of 7) (continued) b a l l ref 82562ez(ex) pin name 82547GI(ei) pin name signal name difference? 82562ez(ex) connection? pop option required? comment
82562ez(ex)/82547GI(ei) dual footprint design guide 38 f11 vss vss x f12 nc nc x f13 nc mdi[2]+ x f14 nc mdi[2]- x g1 nc ci_clk x g2 nc ci[9] x g3 nc nc x g4 nc csa_1.2v x g5 vccr 1.2 v x x x 3.3 v / 1.2 v plane g6 vcc 1.2 v x x x 3.3 v / 1.2 v plane g7 vss vss x g8 vss vss x g9 vss vss x g10 vss vss x g11 vss vss x g12 nc 1.8 v x g13 vcc analog_1.2v x x x 3.3 v / 1.2 v plane g14 vss analog_vss x h1 nc ci[10] x h2 nc csa_vss x h3 nc ci[8] x h4 nc csa_1.2v x h5 vccr 1.2 v x x x 3.3 v / 1.2 v plane h6 vcc 1.2 v x x x 3.3 v / 1.2 v plane h7 vcc 1.2 v x x x 3.3 v / 1.2 v plane h8 vcc 1.2 v x x x 3.3 v / 1.2 v plane h9 vss vss x h10 vss vss x h11 3.3 v analog_1.2v x x x 3.3 v / 1.2 v plane h12 nc nc x h13 nc mdi[3]+ x h14 nc mdi[3]- x j1 nc ci[0] x table 14. ball number to signal mapping (sheet 4 of 7) (continued) b a l l ref 82562ez(ex) pin name 82547GI(ei) pin name signal name difference? 82562ez(ex) connection? pop option required? comment
82562ez(ex)/82547GI(ei) dual footprint design guide 39 j2 nc ci[1] x j3 nc ci[2] x j4 nc csa_1.2v x j5 vccr 1.2 v x x x 3.3 v / 1.2 v plane j6 vcc 1.2 v x x x 3.3 v / 1.2 v plane j7 vcc 1.2 v x x x 3.3 v / 1.2 v plane j8 vcc 1.2 v x x x 3.3 v / 1.2 v plane j9 vcc 1.2 v x x x 3.3 v / 1.2 v plane j10 vcc 1.2 v x x x 3.3 v / 1.2 v plane j11 vcc 1.2 v x x x 3.3 v / 1.2 v plane j12 nc aux_pwr x j13 nc 1.8 v x j14 x2 xtal2 x k1 nc ci[3] x k2 vss csa_vss x k3 vcc 3.3 v x k4 vcc 3.3 v x x x connected to 3.3 v k5 vcc 1.2 v x x x 3.3 v / 1.2 v plane k6 vcc 1.2 v x x x 3.3 v / 1.2 v plane k7 vcc 1.2 v x x x 3.3 v / 1.2 v plane k8 vcc 1.2 v x x x 3.3 v / 1.2 v plane k9 vcc 1.2 v x x x 3.3 v / 1.2 v plane k10 vcc 1.2 v x x x 3.3 v / 1.2 v plane k11 vcc 1.2 v x x x 3.3 v / 1.2 v plane k12 vss analog_vss x k13 vcc 3.3 v x k14 x1 xtal1 x l1 nc ci_strs x l2 nc ci_strf x l3 nc ci[4] x l4 vcc 1.2 v x x x 3.3 v / 1.2 v plane l5 vcc 1.2 v x x x 3.3 v / 1.2 v plane l6 vss vss x x x connected to vss table 14. ball number to signal mapping (sheet 5 of 7) (continued) b a l l ref 82562ez(ex) pin name 82547GI(ei) pin name signal name difference? 82562ez(ex) connection? pop option required? comment
82562ez(ex)/82547GI(ei) dual footprint design guide 40 l7 adv10 nc x x x 82562ez: no connect. internal pull-down. 82547GI(ei): no connect. l8 nc nc x l9 vcc 1.2 v x x x 3.3 v / 1.2 v plane l10 vcc 1.2 v x x x 3.3 v / 1.2 v plane l11 vss vss x l12 nc jtag_tms x l13 jtxd[1] jtag_trst# x x x 82562ez: ich lan connect. 82547GI(ei): jtag connect. l14 jtxd[2] jtag_tck x x x 82562ez: ich lan connect. 82547GI(ei): jtag connect. m1 nc ci[6] x m2 nc ci[5] x m3 nc csa_vss x m4 nc csa_1.2v x m5 nc 1.2 v x m6 vss vss x m7 nc nc x m8 nc nc x m9 nc flsh_ce# x m10 nc eesk x m11 nc flsh_si x m12 jrxd[2] sdp[3] x x x 82562ez: ich lan connect. 82547GI(ei): no connect. m13 jrstsync jtag_tdi x x x 82562ez: ich lan connect. 82547GI(ei): jtag connect. m14 jtxd[0] jtag_tdo x x x 82562ez: ich lan connect. 82547GI(ei): jtag connect. n1 vss csa_vss x table 14. ball number to signal mapping (sheet 6 of 7) (continued) b a l l ref 82562ez(ex) pin name 82547GI(ei) pin name signal name difference? 82562ez(ex) connection? pop option required? comment
82562ez(ex)/82547GI(ei) dual footprint design guide 41 n2 nc ci[7] x n3 nc ci_rcomp x n4 nc ci_vref x n5 nc 1.2 v x n6 vcc 3.3 v x n7 nc nc x n8 vcc 3.3 v x n9 nc flsh_sck x n10 nc eedo x n11 nc nc x n12 vssp vss x n13 jrxd[1] sdp[2] x x x 82562ez: ich lan connect. 82547GI(ei): no connect. n14 jclk sdp[0] x x x 82562ez: ich lan connect. 82547GI(ei): no connect. p1 nc nc p2 vcc 3.3 v x p3 nc ci_swing x p4 nc nc x p5 nc nc x p6 nc nc x p7 nc eecs x p8 vss vss x p9 nc flsh_so/ lan_disable# x p10 nc eedi x p11 nc ctrl12 x p12 3.3 v 3.3 v x p13 jrxd[0] sdp[1] x x x 82562ez: ich lan connect. 82547GI(ei): no connect. p14 nc nc table 14. ball number to signal mapping (sheet 7 of 7) (continued) b a l l ref 82562ez(ex) pin name 82547GI(ei) pin name signal name difference? 82562ez(ex) connection? pop option required? comment
82562ez(ex)/82547GI(ei) dual footprint design guide 42 note: this page is intentionally left blank.
82562ez(ex)/82547GI(ei) dual footprint design guide 43 7.0 dual footprint reference schematic the following pages illustrate a dual purpose 10/100 and 10/100/1000 design using the 82562ez(ex) platform lan connect device and the 82547GI(ei) gigabit ethernet controller.
82562ez(ex)/82547GI(ei) dual footprint design guide 44 o h w q , 5 u h o o r u w q r & ; ( = ( h k w j q l v x q h k z \ o q r w q h q r s p r f v l k w o o d w v q , u h o o r u w q r & , ( , * h k w j q l v x q h k z \ o q r w q h q r s p r f v l k w o o d w v q , y h 5 , ( , * ; ( = ( 1 * , 6 ( ' ( & 1 ( 5 ( ) ( 5 ; ( ' 1 , ( * $ 3 h j d 3 h o w l 7 v h f d i u h w q , * $ 7 - p r u s ( ( k v d o ) w h q u h k w ( v x % 0 6 , + , ( , * v h f d i u h w q , w f h q q r & 1 $ / g q d p r u s ( ( w h q u h k w ( ; ( = ( v q l s g h y u h v h 5 g q d h g r 0 w v h 7 i h 5 9 u h z r 3 ; ( = ( , ( , * u r w f h q q r & - 5 n f d - j d 0 ( ) $ 1 $ / v s d f v v d s \ e g q d v u r w d o x j h 5 u d h q l / u r w f h q q r & - 0 ( ) $ 1 $ / h w d q u h w o $ , ( , * ; ( = ( q j l v h ' i h 5 $ %
82562ez(ex)/82547GI(ei) dual footprint design guide 45 o h w q , 5 -7$*/&, 6'3-rugdq,) /('v 60%xv 6huldo)/$6+ ((3urp (wkhuqhw3ruw &6$3ruw k f w l 3 p p $ * % p p [ p p , ( , * ; ( = ( v s e 0 u h o o r u w q r & w h q u h k w ( k w l z j q l p d h u w 6 v q r l w d f l q x p p r & h u x w f h w l k f u $ $ 6 & h g r f h ' h p d 1 q l 3 h p d 1 o d q j l 6 , ( , * h p d 1 o d q j l 6 ; ( = ( i r g h w u h v v d h e w r q g o x r k v 7 6 5 b 0 6 5 v o l d u u h z r s 1 $ / h k w u h w i d v p o l w q x h o e d w v h u d . / & % 0 6 g q d $ 7 $ ' % 0 6 h k w w d k w h u x v q ( k w l z k j l k f l j r o r w g h o o x s h u d v h f d u w q r h u h k z h p r v v u r w v l v h u s x o o x s n d h z u d q d o s u r & , 1 h k w + & , r w h w x r 5 o d q j l 6 2 , 3 * 0 2 5 3 ( ( , 3 6 q l s q r l w f q x i l w o x p d v l % q l 3 h g r p % 0 6 q l w u h o $ % 0 6 q l d u g q h s 2 h g r p ) 6 $ q l o d q j l v ' 2 2 * b 5 : 3 b , & 3 0 2 5 3 ( ( h u l z r u f l 0 f l j r / * $ 7 - r w h w x r 5 h f d i u h w q , w f h q q r & 1 $ / h w x r 5 u h o o r u w q r f + & , r w h f l y h g p r u s ( ( h q r \ o q r h w d o x s r 3 u r w q h p h j d q d p q r q u r i h u l z r u f l 0 w u r s s x v ) 6 $ u r i , 3 6 q h k z p r u s ( ( h w d o x s r s w r q r ' p r u s ( ( h v 8 ; ( = ( h k w j q l v x h f l y h g + & , h k w k w l z g h w d l f r v v d v h v r s u x s j q l w v h w u r j x e h g o d l f h s v u r i \ o q r o o d w v q , h u l z r u f l 0 j q l v x i l 5 o o d w v q , v h f l y h g 0 2 5 3 ( ( o r f r w r u s , 3 6 j q l v x i l 5 o o d w v q , v h f l y h g 0 2 5 3 ( ( ( 0 3 h x t l q x d v g h h q h f d i u h w q , $ 6 & h k 7 h w d u h s h v d q r v h g l v h u w l h v x d f h e w h q w q h p j h v h j g l u e , & 3 r w , & 3 h f d i u h w q , $ 6 & h w x r 5 u h o o r u w q r & + & 0 r w , ( , * ; ( = ( q j l v h ' i h 5 % $ u h o o r u w q r & , ( , * h k w j q l v x q h k z \ o q r w q h q r s p r f v l k w o o d w v q , u h o o r u w q r & ; ( = ( h k w j q l v x q h k z \ o q r w q h q r s p r f v l k w o o d w v q , 7 ' ohm ohm !ddancapacitorbetween6ccand'nd forboththe30)and-icrowire%%02/-s
82562ez(ex)/82547GI(ei) dual footprint design guide 46 intel r 82562ez/ex - 82547GI/ei 10/100/1000 mbps ethernet controller with communications streaming architecture (csa) vdd pins vss pins reserved pins reserved pins 2 of 2 pin name decode = 82562ez/ex signal name - 82547GI/ei signal name 15mm x 15mm bga 1mm pitch place these capacitors close to their respective pins of the 82547GI(ei). place these capacitors close to the divider network. internal phy clock test point. ieee conformance testing. place this capacitor close to it's respective pin of the 82547GI(ei). 82562ez/ex - 82547GI/ei ref. design d/t install this component only when using the 82562ez/ex controller install this component only when using the 82547GI/ei controller a b install only for special debug or testing purposes
82562ez(ex)/82547GI(ei) dual footprint design guide 47 o h w q , 5 v h v r s u x s j q l w v h w u r j x e h g o d l f h s v u r i \ o q r o o d w v q , % $ f v l k w o o d w v q , j q l v x q h k z \ o q r w q h q r s p ru h o o r u w q r & , ( , * h k w f v l k w o o d w v q , j q l v x q h k z \ o q r w q h q r s p r u h o o r u w q r & ; ( = ( h k w 7 ' , ( , * ; ( = ( q j l v h ' i h 5 24ermination 24ermination 24ermination 24ermination * 2 * 2 * 2 * 2 * 2 * 2 * 2 * 2 3+<,qwhuidfhzlwk ,qwhjudghg0djqhwlfv 5- )ruwkh(=(;gliihuhqwldo sdluvduhwhuplqdwhgxvlqj rkpuhvlvwruv $ $ $ $ $ $ $ $ 7'3 5'1 7'1 5'3 $ $ $ $ %,&2/2563(('/(' 7khvhwkuhhfdsdflwruv dfurvvwkh&+$66,6b*1' wr*1'vsolwduhorfdwhgderyh wkhpdjqhwlfvprgxoh3odfh dvforvhdvsrvvleohwrwkh pdjqhwlfvprgxoh 7khvhwkuhhfdsdflwruv dfurvvwkh&+$66,6b*1' wr*1'vsolwduhorfdwhgehorz wkhpdjqhwlfvprgxoh3odfh dvforvhdvsrvvleohwrwkh pdjqhwlfvprgxoh $ $ r v o d u r w f h q q r & v q l 3 v w u r s % 6 8 v h g x o f q l o r e p \ v v l k w q r q z r k v w r q u r w f h q q r & h o e l w d s p r & v s e 0 q z r k v w r q v w u r 3 % 6 8 q r l v u h y *e( /,1.$&7,9,7</(' 1 $ / 5 ( 3 3 2 & % 9&&
82562ez(ex)/82547GI(ei) dual footprint design guide 48 intel r install only for special debug or testing purposes b a install this component only when using the 82547GI/ei controller install this component only when using the 82562ez/ex controller d/t 82562ez/ex - 82547GI/ei ref. design this lan_disable circuit is for the 82562ez(ex) only. rsm_rst# should not be asserted until 50 ms after the lan power rails are stable. note: for the 82562ez(ex) the bios must delay driving lan_rst# for 20ms after resetting the ich. use the and gate shown if this timing is not already accounted for in your design. choose super io pin that defaults to input on power up and is powered from the resume (aux) well linear regulators: stuff only for 82547GI(ei) bypass caps for 1.2v corevdd place close to lan silicon if alerting is supported, vcc3_3 is sourced fro m either pci_aux_3.3v or the planar 3.3v_stby. otherwise vcc3_3 can be sourced from a non-standby 3.3v power rail. vcc3_3 supply note:
82562ez(ex)/82547GI(ei) dual footprint design guide 49 57huplqdwlrq 57huplqdwlrq 57huplqdwlrq 57huplqdwlrq - 5 - 5 - 5 - 5 - 5 - 5 - 5 - 5 o h w q , 5 v h v r s u x s j q l w v h w u r j x e h g o d l f h s v u r i \ o q r o o d w v q , % $ u h o o r u w q r & , ( , * h k w j q l v x q h k z \ o q r w q h q r s p r f v l k w o o d w v q , u h o o r u w q r & ; ( = ( h k w j q l v x q h k z \ o q r w q h q r s p r f v l k w o o d w v q , 7 ' , ( , * ; ( = ( q j l v h ' i h 5 u r w f h q q r & h o e l w d s p r & v s e 0 q z r k v w r q v w u r 3 % 6 8 q r l v u h y j l * . & $ - * $ 0 d h v x w r q r g v q j l v h g u r ) v u r w l f d s d f s d w u h w q h f v d k w d k w r v o d u r w f h q q r & v q l 3 v w u r s % 6 8 v h g x o f q l o r e p \ v v l k w q r q z r k v w r q 1 $ / 5 ( 3 3 2 & 3 8 . 1 , / q h h u * v w q h q r s p r f h v h k w h f d o 3 u h o o r u w q r & 1 $ / h k w r w h v r o f ' ( / < 7 , 9 , 7 & $ < 7 , 9 , 7 & $ ; 5 ; 7 * 1 , . 1 , / % v s e 0 n q l / i i 2 v s e 0 n q l / q h h u * v s e 0 n q l / h j q d u 2 u r w f h q q r f i r v s d w u h w q h & g h w f h q q r f h e w v x p v f l w h q j d p q h k z o l d u u h z r s y & & 9 r w u h o o r u w q r f , ( , * h k w j q l v x - 0 j q l v 8 ( ) $ h w d q u h w o $ .ote&orthe')%)differential pairsareterminatedusing ohmresistors 7'3 5'1 7'1 5'3
82562ez(ex)/82547GI(ei) dual footprint design guide 50 note: this page intentionally left blank.
82562ez(ex)/82547GI(ei) dual footprint design guide 51 appendix a measuring lan reference frequency using a frequency counter a.1 background to comply with ieee specifications for 10/100 mb ps and 10/100/1000base-t ethernet lan, the transmitter reference frequency must be correct and accurate within 50 parts per million (ppm). note: intel recommends a frequency tolerance of 30 (ppm). most intel lan devices will operate properly with a 25.000 mhz reference crystal, provided it meets the recommended requirements for frequenc y stability, equivalent series resistance at resonance (esr), and load capacitance. most circuits for series resonant crystals includ e two discrete capacitors (typically c1 and c2), with values between 5 pf and 36 pf. the most accurate way to determine the appropriate va lue for the discrete capac itors is to install the approximately correct values for c1 and c2. next, a frequency counter should be used to measure the transmitter reference frequency (or transmitter reference clock). if the transmitter reference frequency is more than 20 ppm below the target frequency, then the values for c1 and c2 are too big and should be decreased. if the transmitter reference frequency is more than 20 ppm above the target frequency, then the values for c1 and c2 are too small and should be increased. this appendix provides instructions and illustrations that explain how to use a frequency counter and probe to determine the ethernet lan device tr ansmit center frequency. an example describing how to calculate the frequency accuracy of the measured and averaged center frequency with respect to the target center frequency is also included. a.2 required test equipment tektronix cmc-251, or similar high resolution, digital counter tektronix p6246, or similar high bandwidth, low capacitance (less than 1 pf) probe tektronix 1103, or similar probe power supply or probe amplifier bnc, 50-ohm coaxial cable (less than 6 feet long) system with power supply and test software for the lan circuit to be tested
82562ez(ex)/82547GI(ei) dual footprint design guide 52 a.3 indirect probing method the indirect probing test method is applicable foremost devices that support 100base-t. since probe capacitance can load the reference crystal an d affect the measured frequency, the preferred method is to use the indirect probing test method when possible. almost all intel lan silicon that support 1000base-t ethernet can provide a buffered 125 mhz clock, which can be used for indirect probing of the transmitter reference clock. the buffered 125 mhz clock will be a 5x multiple of the crystal circuit?s reference frequency ( figure 11 ). different lan devices may require different register settings, to enable the buffered 125 mhz reference frequency. please obtain the settings or instructions that are appropriate for the lan controller you are using. figure 11. indirect probing setup p6246 or similar high impedance probe with less than 1 pf 2-pin header lan silicon ieee test out + lan silicon ieee test out - ch.1 ch.2 input input tektronix 1103 probe power supply 50 ohm input tektronix cmc251 or a similar capability frequency counter 125.00047 50 ohm coaxial cable
82562ez(ex)/82547GI(ei) dual footprint design guide 53 a.4 indirect frequency measurement and frequency accuracy calculation steps 1. make sure the system bios has the lan controller enabled. 2. connect the test equipment as shown in figure 11 . 3. using the appropriate controls for your model of high resolution digital counter, make sure it can display ~125.0000 mhz with at least four decimal places frequency resolution. 4. enable the 125 mhz buffered referen ce clock. an example can be found in appendix b, ?gigconf.exe register settings for 82547GI(ei) devices? . 5. determine the center reference frequency as accurately as possible. this can be done by taking 30 to 50 different readings using the frequency counter and then calculating the average results of the readings. 6. calculate the accuracy of the measured and aver aged center frequency with respect to an ideal 125.0000 mhz reference frequency. where x = average measured frequency in hertz and y = ideal reference frequency in hertz example 1. given: the measured averaged center frequency is 124.99942 mhz (or 124,999,420 hertz). frequencyaccuracy ppm () xy ? () y 1000000 ? () -------------------------------- = frequencyaccuracy ppm () 124999420 125000000 ? () 125000000 1000000 ? () ---------------------------------------------------------------- 4.64 ppm ? = =
82562ez(ex)/82547GI(ei) dual footprint design guide 54 example 2. given: the measured averaged center frequency is 125.00087 mhz (or 125,000,870 hertz). note: the following items should be noted for an ideal reference crystal on a typical printed circuit board. if the transmitter reference frequency is more th an 8 ppm below the target frequency, then the values for c1 and c2 are too big and they sh ould be decreased. when tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. if the transmitter reference frequency is more th an 8 ppm above the target frequency, then the values for c1 and c2 are too small and they should be increased. when tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. a.5 direct probing test method, applicable for most 10/100 devices (devices that do not support 1000base-t) because probe capacitance can load the reference crystal affecting the measured frequency, it is preferable to use a probe w ith less than 1 pf capacitance. note: direct probing is not recommended for the 82547GI(ei) lan silicon. the probe should be connected between the x2 (or xout) pin of the lan device and a nearby ground. typically, it is possible to connect the prob e pins across one of the discrete load capacitors (c2 in figure 12 ). frequencyaccuracy ppm () 125000870 125000000 ? () 125000000 1000000 ? () ---------------------------------------------------------------- 6.96 ppm = =
82562ez(ex)/82547GI(ei) dual footprint design guide 55 figure 12. direct probing method a.6 direct frequency measurement and frequency accuracy calculation steps 1. make sure the system bios has the lan controller enabled. 2. connect the test equipment as shown in figure 12 . 3. using the appropriate controls for your model of high resolution digital counter, make sure it can display ~25.0000 mhz with at least four decimal places frequency resolution. 4. ensure the lan circuits are powered. 5. determine the center reference frequency as accurately as possible. this can be done by taking 30 to 50 different readings using the frequency counter and then calculating the average results of the readings. 6. calculate the accuracy of the measured and aver aged center frequency with respect to an ideal 25.0000 mhz reference frequency.
82562ez(ex)/82547GI(ei) dual footprint design guide 56 where x = average measured frequency in hertz and y = ideal reference frequency in hertz example 3. given: the measured averaged center frequency is 24.99963 mhz (or 24,999,630 hertz). example 4. given: the measured averaged center frequency is 25.00027 mhz (or 25,000,270 hertz). note: the following items should be noted for an ideal reference crystal on a typical printed circuit board. if the transmitter reference frequency is more th an 8 ppm below the target frequency, then the values for c1 and c2 are too big and they sh ould be decreased. when tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. if the transmitter reference frequency is more th an 8 ppm above the target frequency, then the values for c1 and c2 are too small and they should be increased. when tests are performed across temperature, it may be acceptable for the center frequency deviation to be a little greater than 8 ppm. frequencyaccuracy ppm () xy ? () y 1000000 ? () -------------------------------- = frequencyaccuracy ppm () 24999630 25000000 ? () 25000000 1000000 ? () ---------------------------------------------------------- 14.8 ppm ? = = frequencyaccuracy ppm () 25000270 25000000 ? () 25000000 1000000 ? () ---------------------------------------------------------- 10.8 ppm = =
82562ez(ex)/82547GI(ei) dual footprint design guide 57 appendix b gigconf.exe register settings for 82547GI(ei) devices the following steps describe the indirect probing test method using gigconf.exe for 82547GI(ei) devices. 1. boot to dos using a dos boot diskette . 2. launch gigconf from the diskette (gigconf.exe) . 3. select the intel network connection to be measured . a. if multiple adapters are installed, use the arrow keys to navigate to highlight the selected adapter and press enter. 4. select registers by pressing ?r?. 5. select phy registers by pressing ?p ?. 6. use the arrow keys to navigate to the value listed next to address 0000 . 7. press enter when the value is highlighted an d then use backspace to clear out the current value . 8. type ?0100? for the value and then press enter. 9. navigate to the value listed next to address 0012 . 10. press enter to select the highlighted valu e and use backspace to clear the current value . 11. type ?8000? for the value and then press enter. 12. navigate to the set address field on the right side of the screen (use the right arrow key) 13. press enter to select the highlighted value and then use backspace to clear out the current value . 14. type ?4011? for the value and then press enter. this changes the phy register screen and updates it with new addresses and values. 15. use the arrow keys to navigate to the value for address 4011. 16. press enter when the value is highlighted an d then use backspace to clear the current value . 17. type ?8000? for the value and then press enter. 18. use the right arrow key to navigate to the set address field on the right side of the screen . 19. press enter when the value is highlighted and use backspace to clear the current value. 20. enter ?2f5b? (capital letters are not requ ired) for the address and then press enter. 21. use the arrow keys to navigate to the value for address ?2f5b?. 22. press enter when the value is highlighted an d then use backspace to clear the current value. 23. type ?0003? for the value and then press enter. 24. use the right arrow key to navigate to the set address field on the right side of the screen . 25. press enter when the value is highlighted an d then use backspace to clear the current value .
82562ez(ex)/82547GI(ei) dual footprint design guide 58 note: this page intentionally left blank.

▲Up To Search▲

Price & Availability of 82547GI

	To Download 82547GI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .